..........................................................................................-55°C to +125°C
Storage Temperature Range ..............................................................................................-55°C to +125°C
Solder Temperature .......................................................Refer to the IPC/JEDEC J-STD-020 Specification.
These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(-55°C to +125°C; VDD=3.0V to 5.5V)
PARAMETER SYMBOL CONDITIONS
MIN
TYP
MAX UNITS
NOTES
Supply Voltage
VDD Local
Power +3.0
+5.5
V
1
Pullup Supply
Parasite Power
+3.0
+5.5
V
V 1,2
Voltage
PU
Local Power
+3.0
VDD
Thermometer
-10°C to +85°C
±0.5
t
°C 3
Error
ERR
-55°C to +125°C
±2
Input Logic-Low
VIL
-0.3
+0.8
V 1,4,5
Local Power
+2.2
The lower of
5.5
Input Logic-High
VIH
V 1,
6
or
Parasite Power
+3.0
VDD + 0.3
Sink Current
IL
VI/O = 0.4V
4.0
mA
1
Standby Current
IDDS
750 1000
nA 7,8
Active Current
IDD
VDD = 5V
1
1.5
mA
9
DQ Input Current
IDQ
5
μA
10
Drift
±0.2
°C
11
NOTES:
1) All voltages are referenced to ground.
2) The Pullup Supply Voltage specification assumes that the pullup device is ideal, and therefore the high level of the pullup is equal to VPU. In order to meet the VIH spec of the DS18B20, the actual supply rail for the strong pullup transistor must include margin for the voltage drop across the transistor when it is turned on; thus: VPU_ACTUAL = VPU_IDEAL + VTRANSISTOR.
3) See typical performance curve in Figure 17.
4) Logic-low voltages are specified at a sink current of 4mA.
5) To guarantee a presence pulse under low voltage parasite power conditions, VILMAX may have to be reduced to as low as 0.5V.
6) Logic-high voltages are specified at a source current of 1mA.
7) Standby current specified up to +70°C. Standby current typically is 3μA at +125°C.
8) To minimize IDDS, DQ should be within the following ranges: GND ≤ DQ ≤ GND + 0.3V or VDD – 0.3V ≤ DQ ≤ VDD.
9) Active current refers to supply current during active temperature conversions or EEPROM writes.
10) DQ line is high (“high-Z” state).
11) Drift data is based on a 1000-hour stress test at +125°C with VDD = 5.5V.
19 of 22
DS18B20
AC ELECTRICAL CHARACTERISTICS—NV MEMORY
(-55°C to +100°C; VDD = 3.0V to 5.5V)
PARAMETER SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NV Write Cycle Time
tWR
2 10
ms
EEPROM Writes
NEEWR
-55°C to +55°C
50k
writes
EEPROM Data Retention
tEEDR
-55°C to +55°C
10
years
AC ELECTRICAL CHARACTERISTICS (-55°C to +125°C; VDD = 3.0V to 5.5V)
PARAMETER SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
9-bit resolution
93.75
Temperature Conversion
10-bit resolution
187.5
t
ms 1
Time
CONV
11-bit resolution
375
12-bit resolution
750
Start Convert T
Time to Strong Pullup On
tSPON
10 μs
Command Issued
Time Slot
tSLOT
60 120 μs
1
Recovery Time
tREC
1
μs
1
Write 0 Low Time
tLOW0
60 120 μs
1
Write 1 Low Time
tLOW1
1 15 μs
1
Read Data Valid
tRDV
15 μs
1
Reset Time High
tRSTH
480
μs
1
Reset Time Low
tRSTL
480
μs
1,2
Presence-Detect High
tPDHIGH
15
60
μs
1
Presence-Detect Low
tPDLOW
60 240 μs
1
Capacitance CIN/OUT
25
pF
NOTES:
1) See the timing diagrams in Figure 18.
2) Under parasite power, if tRSTL > 960μs, a power-on reset may occur.
Figure 17. Typical Performance Curve
DS18B20 Typical Error Curve
0.5
) 0.4
+3s Error
0.3
0.2
0.1
0
-0.1 0
10
20
30
40
50
60
70
-0.2
Thermometer Error (°C -0.3
Mean Error
-0.4
-3s Error
-0.5
Temperature (°C)
20 of 22
DS18B20
Figure 18. Timing Diagrams
21 of 22
DS18B20
REVISION HISTORY
REVISION
PAGES
DESCRIPTION
DATE
CHANGED
In the Absolute Maximum Ratings section, removed the reflow oven 030107
temperature value of +220°C. Reference to JEDEC specification for reflow 19
remains.
In the Operation—Alarm Signaling section, added “or equal to” in the 5
desciption for a TH alarm condition
101207
In the Memory section, removed incorrect text describing memory.
7
In the Configuration Register section, removed incorrect text describing 8
configuration register.
In the Ordering Information table, added TO-92 straight-lead packages and 042208
included a note that the TO-92 package in tape and reel can be ordered with 2
either formed or straight leads.
22 of 22
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.